1. Technical Field
The present disclosure relates to a semiconductor memory device, and more particularly, to a method of improving redundancy efficiency in a semiconductor memory device.
2. Discussion of the Related Art
The manufacture of different types of semiconductor memory chips has been combined in order to reduce development and mass production costs. For example, both a memory chip using memory cells for storing error checking/correcting codes (ECCs) and a memory chip not using ECC memory cells have been simultaneously manufactured. As a result, labor and expenses can be reduced as compared to cases where the chips are individually formed.
When a first memory chip using ECC cells and a second memory chip not using ECC cells are simultaneously formed, the ECC cells in the second memory chip are dummy cells because, although they occupy an area of the second memory chip, they are not used.
FIG. 1 is a schematic block diagram of a conventional semiconductor memory device 100. Referring to FIG. 1, the semiconductor memory device 100 includes a plurality of memory banks. FIG. 1 illustrates the semiconductor memory device 100 including four memory banks 110, 120, 130, and 140. Each of the memory banks 110, 120, 130, and 140 include a NOR cell block NOR, and an ECC cell block ECC.
The NOR cell block NOR may include memory cells, in which data (e.g., other than ECC data) is stored, and redundancy memory cells which substitute for defective memory cells. The ECC cell block ECC includes ECC memory cells in which ECC data (e.g., error checking/correcting codes) is stored.
FIG. 2 is a block diagram of one memory bank 110 of the semiconductor memory device in FIG. 1. Referring to FIG. 2, the memory bank 110 includes a plurality of normal or first level cell blocks B1 through B5, a plurality of redundancy cell blocks RD1 through RD5, and an ECC cell block ECC. The modifier “normal” for purposes of this disclosure is being used to distinguish between first level cell blocks, memory cells and components associated therewith and remaining cell blocks, memory cells and components associated therewith. For example, redundancy cell blocks and memory cells can substitute for “normal” cell blocks and memory cells that become defective. The NOR cell block NOR of FIG. 1 includes a plurality of the normal cell blocks B1 through B5, and the plurality of redundancy cell blocks RD1 through RD5.
The normal cell blocks B1 through B5 include memory cells for storing data (referred to as normal memory cells hereinafter). The redundancy cell blocks RD1 through RD5 include redundancy memory cells which substitute for defective normal memory cells, such that when a defect occurs in the normal cell blocks B1 through B5, the redundancy cells in the redundancy cell blocks RD1 through RD5 act substitute for the defective normal memory cells. For example, as shown in FIG. 2, defective memory cells F1, F2, F3, F4 and F5 of the normal cell blocks B1, B2, B3, B4 and B5, respectively may be replaced by redundancy cells R1, R2, R3, R4 and R5 of the redundancy cell blocks RD1, RD2, RD3, RD4 and RD5, respectively.
When the semiconductor memory device 100 shown in FIG. 1 does not use any memory cells for storing ECCs, the ECC cell block ECC becomes a dummy cell block and occupies an area in the semiconductor memory device without performing a specific function. Therefore, there exists a need to utilize the unused ECC cells.